Pixel clock generator and image forming apparatus
US8493578B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 2009 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Apr 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/04794
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel clock generator includes a frequency divider 4 that generates a pixel clock PCLK based on a high frequency clock VCLK, a comparator 5 that calculates an error Lerr in the time obtained by integrating a cycle of the pixel clock PCLK for a target number RefN from a time when synchronization signals SPSYNC and EPSYNC are detected, a filter 6, and a frequency calculating unit 7 that sets a frequency dividing value M of the frequency divider 4. The filter 6 and the frequency calculating unit 7 calculate an average of a frequency of the pixel clock PCLK based on the error Lerr, determine a reference error value from the error Lerr in N-cycles, calculate offset values of the frequencies of N pieces of pixel clocks PCLK based on a difference between the reference error value and the error Lerr, and calculate the frequency dividing value M based on a result obtained by adding the circularly selected offset values and the average of the frequency of the pixel clock PCLK.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.