Memory cell and memory device using the same
US8493768B2 · kind B2 · utility
1Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2011 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Feb 20, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of switching elements are configured to be separately controlled on the basis of the individual control signals so as to prevent each electrode of the ferroelectric transistor from being floated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.