Nonvolatile memory device and erasure method thereof
US8493793B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 2011 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Jan 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method in performing an erasure operation of a nonvolatile memory device includes a step of performing a block erasure operation wherein a plurality of memory cells in a selected block are erased at once, a step of selecting an over-programmed memory cell having a threshold voltage higher than an upper bound verification voltage, and a step of erasing selectively the over-programmed memory cell. A nonvolatile memory device comprises a cell array comprising a plurality of memory cells wherein the memory cells have a desired threshold voltage distribution for a state of being erased, wherein the distribution spreads over between a lower bound verification voltage and an upper bound verification voltage, a voltage generator configured to provide a word line voltage and a bit line voltage to word lines and bit lines of the plurality of memory cells respectively, a write driver and sense amplifier configured to write data or read out data through bit lines of the plurality of memory cells, and a control logic configured to control the voltage generator and the write driver and sense amplifier to perform a post-erasure operation of selecting and erasing an over-programmed memory cell h…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.