Non-volatile memory cell and methods for programming, erasing and reading thereof
US8493794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2011 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Mar 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.