Processor for performing multiply-add operations on packed data
US8495123B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Oct 1, 2012 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Oct 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.