Alignment circuit for parallel data streams
US8495264B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2011 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Apr 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parallel data generated by demultiplexing received serial data such as in a Serial RapidIO (SRIO) data stream can become misaligned as a result of, e.g., clock tolerance compensation (CTC) processing at the receiver. In one embodiment of the invention, the misaligned parallel data is properly aligned based on a mapping from each of a finite number of possible previous alignment conditions (e.g., words A-D) to a corresponding finite number of possible subsequent alignment conditions (e.g., words B-G). The change from a previous alignment condition to a different subsequent alignment condition is recognized by determining the location of start-of-packet (SOP) or start-of-control-symbol (SOC) data in the parallel data stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.