Solid-state storage system with parallel access of multiple flash/PCM devices
US8495471B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2009 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Jan 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/765
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.