Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing
US8495533B2 · kind B2 · utility
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Key dates
| Filing date | Sep 16, 2006 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.