Using direct memory access to initialize a programmable logic device
US8495545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2012 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Jul 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17758
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment includes using direct memory access (DMA) to initialize a programmable logic device (PLD). An aspect of the invention includes manipulating a control line of the PLD to configure the PLD in a programming mode. PLD programming data is received at a PLD interface from a DMA control at a DMA speed. The PLD interface controls access of a processor and the DMA control to a programming port on the PLD. The PLD interface includes a data buffer and pacing logic. The PLD programming data is written to the data buffer and read from the data buffer. The PLD programming data transmitted to the programming port on the PLD at a PLD programming speed. The pacing logic of the PLD interface controls the data transmission at the PLD programming speed, and the DMA control is configured to transform the PLD programming data while the processor performs other processing tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.