Vertical memory devices including indium and/or gallium channel doping
US8497555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2011 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Jan 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
Abstract
A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.