Lattice network for power amplifier output matching
US8497744B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2009 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Jan 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/387
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of circuits, apparatuses, and systems for a lattice matching network are disclosed. Embodiments may include a power amplifier to provide single-ended amplification of a radio frequency signal. A lattice matching network may be coupled with the power amplifier and may transform a source impedance associated with an output of the power amplifier to a load impedance. In some embodiments, the lattice matching network may include first and second arms coupled in parallel between the power amplifier and an output node. The first arm may include a serial high-low network and the second arm may include a serial low-high network. The serial high-low network and the serial low-high network may provide a passband response with respect to the radio frequency signal. The serial high-low network and serial low-high network may include one or more Pi networks. Other embodiments may be described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.