Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
US8497789B2 · kind B2 · utility
2Cited by
8References
14Claims
0Family size
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Key dates
| Filing date | Jun 6, 2012 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Jun 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.