Array structure having thin film transistor and connecting structure for gate line charging and manufacturing method thereof
US8497970B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2011 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Dec 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136272
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate comprises: a base substrate; a display area comprising gate lines and data lines formed on the base substrate, wherein a pixel electrode and a first thin film transistor are formed in each of pixel units defined by the gate lines and the data lines which are crossed with each other, and the gate lines comprises a first gate line and a second gate line; and a dummy area which is at the periphery of the display area, which comprises a second thin film transistor and a connecting structure for each gate line, wherein the first gate line and the second gate line are connected with each other through the second thin film transistor and the connecting structure for the first gate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.