Memory control system and method
US8499126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2011 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Nov 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.