Serial architecture for high assurance processing
US8499163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2010 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Aug 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processing system (60) includes an input interface (62), a first processor (64), a second processor (66), and an output interface (68) arranged in a serial configuration. Each of the input interface (62), first processor (64), second processor (66), and output interface (68) computes a digest (92, 100, 110, and 114) using information, e.g., a unique parameter (94, 102, 112, 118), known only by that element (62, 64, 66, 68) and using information generated by that element (62, 64, 66, 68). The digests (92, 100, 110, and 114) are used to validate the integrity of payload data (86) processed by the system (60) to form processed data (104) and the system (60) only outputs the processed data (104) upon validation of data integrity. The serial configuration of system (60) may be implemented to provide high bit rate, redundant cryptographic services.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.