Memory device and error control codes decoding method
US8499217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2008 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Mar 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.