Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool
US8499262B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 2010 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Sep 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0664
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array. (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.