Process of fabricating semiconductor device with low capacitance for high-frequency circuit protection
US8501580B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Feb 28, 2011 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Feb 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/676
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a semiconductor device includes depositing n-type dopant on a p-type substrate, implanting n-type material into the substrate, and growing an n-type epitaxial layer atop the n+ layer. Trenches surrounding the device region are formed and an n+ layer on the sidewalls of the trenches is formed. The trenches are filled by growing a layer of thermal oxide on the sidewalls of the trenches and deposition of plasma enhanced oxide or polysilicon into the trenches, and planarizing the top surface. n+ region of the device is formed by forming an oxide layer on the top surface of the device layer and etching the oxide, depositing n-type dopant material and driving in by high temperature diffusion. p+ region of the device is formed by etching the oxide, depositing p-type dopant material and driving in by high temperature diffusion so that the breakdown voltage is set for circuit protection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.