Patent · US Active

Semiconductor device with a trench isolation and method of manufacturing trenches in a semiconductor body

US8502308B2 · kind B2 · utility

7Cited by

3References

11Claims

0Family size

Assignee

AMS AG · AT

Inventors

Martin Schrems · Langenbruck, DE
Jong Mun Park · Graz, AT

Key dates

Filing date	May 15, 2007
Grant date	Aug 6, 2013
Priority date	—
Expiry date	Dec 9, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/307
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.