Spintronic devices with integrated transistors
US8503224B2 · kind B2 · utility
3Cited by
41References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2012 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Apr 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.