Suppressing power supply noise using data scrambling in double data rate memory systems
US8503678B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Apr 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/582
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.