Method and apparatus for managing erase count of memory device
US8504760B2 · kind B2 · utility
4Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Sep 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not accessible to users of the data storage cells, and increasing an erase count stored in an erase count storing region of the hidden cell corresponding to at least one erased data storage cell when the at least one data storage cell is erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.