Computer, computer system, and data communication method
US8504780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2011 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Jun 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.