ROM data patch circuit, embedded system including the same and method of patching ROM data
US8504799B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2007 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Jun 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/66
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read only memory (ROM) data patch circuit replaces ROM data stored in N modified ROM data blocks with patch data stored in N random access memory (RAM) patch blocks based on patch information. The ROM data patch circuit includes a data patch detecting unit, a RAM address generating unit, and an address selecting unit. The data patch detecting unit generates N offset select signals and an address select signal. The N offset select signals indicate which block a read ROM address belongs to, and the address select signal represents whether the read ROM address belongs to any of the N modified ROM data blocks. The RAM address generating unit generates a read RAM address corresponding to the read ROM address based on the offset select signals. The address selecting unit outputs one of the read ROM address and the read RAM address based on the address select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.