LDPC decoder and method for LDPC decoding based on layered algorithm applied to parity check matrix
US8504892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Sep 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6566
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.