Translating overlapping states into representative states
US8504933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | May 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer application program can comprise multiple overlapping states associated with functionality or components of the application program. Simultaneous output of all such states can be impractical. Representative states can be defined in terms of the statuses of individual states relevant to a particular representative state. Additionally, representative states can be ranked, where multiple representative states that share the same ranking can overlap with each other, but not with other representative states. To avoid transitioning between states too quickly, and presenting output for too short a time, hysteresis mechanisms can be applied in the form of a set delay, a reset delay or a combination thereof. The duration of the set and reset delay can be established independently of each other and independently for each state. The output can be in accordance with the representative state associated with the current statuses of individual states, accounting for selected hysteresis mechanisms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.