Systems and methods for generating a test environment and test system surrounding a design of an integrated circuit
US8504973B1 · kind B1 · utility
4Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2011 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Oct 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for generating and using a test environment and a test system surrounding a design are described. The systems and methods may involve using a same application software for creating a design and for receiving a selection to generate the test environment and the test system. In response to receiving the selection, the systems and methods may execute a verification tool to create the test environment and test system. Moreover, a user may not fill in templates of components of the verification tool. The verification tool is integrated within the application software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.