Digital phase locked loop circuits with multiple digital feedback loops
US8508266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Dec 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.