Image signal processor line buffer configuration for processing ram image data
US8508612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2010 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Oct 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides techniques relates to the implementation of a raw pixel processing unit using a set of line buffers. In one embodiment, the set of line buffers may include a first subset and second subset. Various logical units of the raw pixel processing unit may be implemented using the first and second subsets of line buffers in a shared manner. For instance, in one embodiment, defective pixel correction and detection logic may be implemented using the first subset of line buffers. The second subset of line buffers may be used to implement lens shading correction logic, gain, offset, and clamping logic, and demosaicing logic. Further, noise reduction may also be implemented using at least a portion of each of the first and second subsets of line buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.