Bufferless routing in on-chip interconnection networks
US8509078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2009 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Apr 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/251
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
As microprocessors incorporate more and more devices on a single chip, dedicated buses have given way to on-chip interconnection networks (“OCIN”). Routers in a bufferless OCIN as described herein rank and prioritize flits. Flits traverse a productive path towards their destination or undergo temporary deflection to other non-productive paths, without buffering. Eliminating the buffers of on-chip routers reduces power consumption and heat dissipation while freeing up chip surface area for other uses. Furthermore, bufferless design enables purely local flow control of data between devices in the on-chip network, reducing router complexity and enabling reductions in router latency. Router latency reductions are possible in the bufferless on-chip routing by using lookahead links to send data between on-chip routers contemporaneously with flit traversals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.