Architecture and system for coordinated network-wide redundancy elimination
US8509237B2 · kind B2 · utility
4Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Dec 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network employing redundancy-aware hardware may actively allocate decompression tasks among different devices along a single path to improve data throughput. The allocation can be performed by a hash or similar process operating on a header of the packets to distribute caching according to predefined ranges of hash values without significant additional communication overhead. Decompression of packets may be similarly distributed by marking shim values to match the earlier caching of antecedent packets. Nodes may use coordinated cache sizes and organizations to eliminate the need for separate cache protocol communications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.