Direct memory access engine physical memory descriptors for multi-media demultiplexing operations
US8509254B2 · kind B2 · utility
3Cited by
5References
18Claims
0Family size
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Key dates
| Filing date | Jun 28, 2010 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Nov 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.