Crest factor reduction with phase optimization
US8509345B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 9, 2009 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | May 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2621
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for reducing peaks comprises a processor and a memory. The processor is configured to determine phase offsets for a plurality of input signals. The phase offsets are determined using trials of phase offsets to determine a selected set of phase offsets. The processor is further configured to modulate the input data signals using the selected set of phase offsets to produce modulated phase offset data signals and to generate a sum of modulated phase offset data signals, such that the sum has a lower peak value as compared to the sum not using the selected set of phase offset signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.