Continuous-rate clock recovery circuit
US8509371B2 · kind B2 · utility
8Cited by
3References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2009 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Mar 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.