Power limiter system
US8509958B2 · kind B2 · utility
5Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2011 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Sep 22, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/76
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power limiter system is described. The power limiter system is configured to receive a phase locked loop (PLL) error signal; analyze the PLL error signal to identify an occurrence of a grid contingency event; generate a first power command signal corresponding to an occurrence of the grid contingency event; and, transmit the first command signal to a converter interface controller. The system further includes a memory configured to store at least one variable that corresponds to the PLL error signal upon identification of an occurrence of the grid contingency event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.