Circuit to efficiently handle data movement within a cache controller or on-chip memory peripheral
US8510493B2 · kind B2 · utility
0Cited by
4References
16Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 27, 2010 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Oct 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.