Smart card chip arrangement
US8511567B2 · kind B2 · utility
0Cited by
4References
12Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Sep 8, 2008 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Sep 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/87
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A smart-card chip arrangement comprises: a smart-card chip (148); an organic semiconductor layer (166, 168, 170, 172) disposed on a surface of the chip, and at least one transistor (150, 152, 154, 156) formed in the organic semiconductor layer. The at least one transistor is configured so as to enable an invasive attack on the chip to be detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.