RF CMOS transistor design
US8513707B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2009 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Nov 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.