Clock delay adjustment circuit for semiconductor integrated circuit and control method of the same
US8514002B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 4, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal adjustment circuit in a semiconductor integrated circuit includes: multiple circuit blocks; multiple clock delay circuits supplying delayed clock signals of the input clock signals under the control of the delay control signals to the corresponding circuit blocks; a control circuit conducting a delay test of the circuit blocks; a recovery group memory circuit storing information in the circuit blocks requiring the delay process among the circuit blocks, responsive to the result of the delay test; delay setting circuits storing information about the delay value for circuit blocks requiring the delay process among the circuit blocks, responsive to the result of the delay test; and a delay setting dispatch control circuit dispatching the delay control signal corresponding to the delay value information stored in the delay setting circuit to the clock delay circuits corresponding to the information about the circuit blocks stored in the recovery group memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.