Single stage and scalable serializer
US8514108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Sep 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.