Programmable linearity correction circuit for digital-to-analog converter
US8514112B2 · kind B2 · utility
3Cited by
5References
30Claims
0Family size
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Key dates
| Filing date | Jun 24, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Aug 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/808
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.