Excess loop delay compensation for a continuous time sigma delta modulator
US8514117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Nov 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.