Method of fabricating array substrate having double-layered patterns
US8514340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2009 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Dec 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136295
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate having double-layered metal patterns for use in a liquid crystal display device and a manufacturing method thereof are disclosed in the present invention. The array substrate includes a gate electrode and a gate line each having a molybdenum alloy (Mo-alloy) layer and a copper (Cu) layer configured sequentially on a substrate; a gate insulation layer on the substrate to cover the gate electrode and the gate line; an active layer arranged on the gate insulation layer in a portion over the gate electrode; an ohmic contact layer on the active layer; a data line on the gate insulation layer, the data line crossing the gate line and defining a pixel region; source and drain electrodes on the ohmic contact layer, the source electrode extending from the data line, and the drain electrode spaced apart from the source electrode; a passivation layer on the gate insulation layer covering the data line and the source and drain electrode, the passivation layer having a drain contact hole exposing a portion of the drain electrode; and a pixel electrode configured on the passivation layer in the pixel region, the pixel electrode electrically contacting the drain electrode throu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.