Technique for verifying the microstructure of lead-free interconnects in semiconductor assemblies
US8514386B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Nov 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B2210/56
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.