Multiple-port memory device comprising single-port memory device with supporting control circuitry
US8514652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Nov 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple-port memory device having at least first and second ports each configured to support read and write operations. The multiple-port memory device further comprises a single-port memory device and control circuitry coupled between the first and second ports and the single-port memory device. The control circuitry is configured to multiplex input signals received over the first and second ports of the multiple-port memory device into respective input time slots of the single port of the single-port memory device, and to demultiplex output time slots of the single port of the single-port memory device into output signals that are supplied over the first and second ports of the multiple-port memory device. In an illustrative embodiment, the single-port memory device operates at a clock rate that is an integer multiple of a clock rate of first and second memory drivers that supply the input signals to and receive the output signals from the respective first and second ports of the multiple-port memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.