Extensible packet processing architecture
US8514855B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2010 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Aug 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technique for distributed packet processing includes sequentially passing packets associated with packet flows between a plurality of processing engines along a flow through data bus linking the plurality of processing engines in series. At least one packet within a given packet flow is marked by a given processing engine to signify by the given processing engine to the other processing engines that the given processing engine has claimed the given packet flow for processing. A processing function is applied to each of the packet flows within the processing engines and the processed packets are output on a time-shared, arbitered data bus coupled to the plurality of processing engines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.