Processing of multiple cells in a network device with two reads and two writes on one clock cycle
US8514875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2006 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Aug 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/1546
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.