Cryptographic processor with dynamic update of encryption state
US8515059B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Mar 30, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Mar 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient implementation of a cryptographic processor that dynamically updates the encryption state is described. The cryptographic processor can be implemented with a minimal number of gates, yet still perform cryptographic operations quickly. The cryptographic processor has an interface, a memory, a pseudorandom permutation block and control logic. The interface receives input data blocks and returns cryptographically processed data blocks. The memory is used to store an encryption state of the cryptographic processor. The pseudorandom permutation block transforms a portion of the encryption state that is modified for each input data block by at least the input data block and a previously transformed data block. The control logic routes data in the cryptographic processor to return cryptographically processed data blocks at the interface and update dynamically the encryption state stored in memory using the transformed data blocks from the pseudorandom permutation block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.