Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface
US8516163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2007 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.