System and method utilizing distributed byte-wise buffers on a memory module
US8516185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2010 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Oct 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.